Prof. Xiaoqing Wen

Kyushu Institute of Technology, Japan

Biography: Xiaoqing Wen received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its Chief Technology Officer until 2003. In 2004, he joined Kyushu Institute of Technology, Japan, where he is currently a Professor and the Chair of the Department of Creative Informatics. He founded Dependable Integrated Systems Research Center in 2015 and served as its Director until 2017. His research interests include VLSI test, diagnosis, and testable design. He co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability (Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (Springer, 2009). He holds 43 U.S. Patents and 14 Japan Patents on VLSI testing. He received the 2008 IEICE-ISS Best Paper Award for his pioneering work on X-filling-based low-capture-power test generation. He is a fellow of the IEEE, a senior member of the IPSJ, and a member of the IEICE. He is serving as associate editors for IEEE Transactions on Computer-Aided Design, IEEE Transactions on VLSI, and the Journal of Electronic Testing: Theory and Applications.

"Power-Aware Testing for Low-Power VLSI Circuits"

Abstract: Low power has become an uncomprisable design requirement for LSI circuits destined for mobile or IoT applications, and numerous hardware/software techniques have been developed for drastically reducing power dissipation in function mode. However, the testing of such low-power LSI circuits is increasingly becoming a severe challenge, especially for at-speed scan testing where a transition is launched at the output of a flip-flop and the corresponding circuit response is captured by a flip-flop within a functional clock cycle in order to test for delay defects. The culprit is excessively high test power compared with functional power, caused by the significant difference between test and functional data and clocking schemes. Excessive test power may cause die/package damage due to excessive heat as well as undue yield loss due to excessive power supply noise on path delay and/or clock trees, as illustrated in the following figure. As a result, it has become imperative to apply power-aware testing to low-power LSI circuits. In order words, low-power LSI circuits cannot be successfully realized without effective and efficient power-aware testing solutions. This paper will highlight three major test-power-induced problems (namely heat, false failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research topics in this field will also be discussed.

Prof. Zhi-Gong Wang

Southeast University, China

Biography: Zhi-Gong Wang was born in Henan, China. He received the M.-Eng. degree in radio engineering from Nanjing Institute of Technology (now, Southeast University), Nanjing, China, in 1981, and the Dr.-Ing. degree in electronic engineering from Ruhr-University Bochum, Germany, in 1990. From 1977 to 1981, he worked on radio communication techniques and computer aided circuit designs in Nanjing Institute of Technology. During 1982-1984 he worked as a lecturer on semiconductor circuit techniques in Tongji-University, Shanghai. From 1985 to 1990, he worked on high-speed silicon bipolar circuit designs for multigigabit/s optic fiber communication in Ruhr-University Bochum, Germany. From Oct. 1990 to Sept. 1997, he has been with Fraunhofer-Institute of Applied Solid State Physics, Freiburg, Germany, working on high-speed GaAs ICs for optic-fiber data transmission and MMICs. Since Oct. 1997, he is full professor of Southeast University, Nanjing, China. He is the author or co-author of 20+ books, 500+ SCI/EI/ISTP-indexed papers, and inventor of 100+ patents of China, Germany, Europe, USA, and Japan. He is Senior Member of IEEE since 1993, CIE-Fellow since 2017, Chairman of the Advisory Committee of Electrical and Electronical Basic Courses of Chinese Universities since 2001. He is Guest/Visiting Professor of 20+ universities of China, Canada, and Australian. Recently, he is involving in IC design for optic-fiber transmission systems, for RF wireless, microwave, and millimeterwave applications, and in micro-electronic systems for bio-medical applications.

"Microelectronic Nerve Bridge for Neural Signal Regeneration and Microelectronic Nerve Antimissile System for Neural Signal Block"

Abstract: In the world there are more than 100 million patients who suffer from different neural deseases such as stroke, Parkinson's disease (PD), cerebral palsy, spinal cord injury (SCI), and so on. Of those patients, two states of the neural signal are divided: interrupt or abnormal. For the interrupt state, we have conceptualized the technique called microelectronic nerve bridge (MENB), and for the abnormal state, the techinique called microelectronic nerve antimissile system (MENAS). The function of the MENB is to regenerate the interrupted neural signal and let the related neural function rebuilding, while function of the MENAS is to eliminate the abnormal neural signals and let the spastic muscle keep rest. In this talk, the principles, the system constructions, and the experimental results of both MENB and MENAS are given.

Assoc. Prof. Chung-An Shen

Taiwan University of Science and Technology (NTUST), Taiwan

Biography: Chung-An Shen received the B.Sc. degree from Taiwan University of Science and Technology (NTUST), Taipei, Taiwan in 2000, the M.Sc. degree from the Ohio State University, Columbus, OH, USA in 2003, and the Ph.D. degree from the University of California, Irvine in 2012. He joined the Department of Electronic and Computer Engineering at NTUST in 2012, where he is currently an Associate Professor. Dr. Shen’s research interests are in efficient digital circuits and systems designs with focus on signal processing applications. Specifically, Dr. Shen has published more than 30 papers in designing circuits and systems for wireless communication, networking, and multimedia processing systems. In addition, Prof. Shen has served as one of the handling editors for the Journal of Circuits, Systems, and Computers, and has been in the technical committees for several international conferences. Before the academic career, Dr. Shen also held several industry positions in the area of signal processing and wireless system design including Texas Instruments Inc. and Qualcomm Inc.

"The Algorithm and VLSI Architecture of a High Efficient Motion Estimation with Adaptive Search Range for HEVC Systems"

Abstract: This talk presents a novel algorithm and VLSI architecture of Motion Estimation (ME) for High Efficiency Video Coding (HEVC) systems. The proposed algorithm examines a much smaller set of search candidates and thus greatly reduces the computational complexity. Furthermore, in order to strike a balance between the quality of the Video and the efficiency of the system, this algorithm possesses the advantages that the number of search candidates is adaptive to the characteristic of the Video content. The simulation results show that, compared to the HM reference software, the proposed algorithm leads to a 96% reduction of search candidates with only 1.98% increment of average bitrate. Based on this algorithm, a hardware-efficient VLSI architecture of ME is designed and implemented with 90nm technology. The experimental results show that, occupying the area complexity of 274.5 kGE, the presented design achieves 60 frames per second (fps) with resolution of 3840×2160 at the frequency of 201 MHz. The proposed ME system enhances the hardware efficiency by at least 50% compared to the prior works.