Prof. Xiaoqing Wen
Kyushu Institute of Technology, Japan
Biography: Xiaoqing Wen received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its Chief Technology Officer until 2003. In 2004, he joined Kyushu Institute of Technology, Japan, where he is currently a Professor and the Chair of the Department of Creative Informatics. He founded Dependable Integrated Systems Research Center in 2015 and served as its Director until 2017. His research interests include VLSI test, diagnosis, and testable design. He co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability (Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (Springer, 2009). He holds 43 U.S. Patents and 14 Japan Patents on VLSI testing. He received the 2008 IEICE-ISS Best Paper Award for his pioneering work on X-filling-based low-capture-power test generation. He is a fellow of the IEEE, a senior member of the IPSJ, and a member of the IEICE. He is serving as associate editors for IEEE Transactions on Computer-Aided Design, IEEE Transactions on VLSI, and the Journal of Electronic Testing: Theory and Applications.
"Power-Aware Testing for Low-Power VLSI Circuits"
Abstract: Low power has become an uncomprisable design requirement for LSI circuits destined for mobile or IoT applications, and numerous hardware/software techniques have been developed for drastically reducing power dissipation in function mode. However, the testing of such low-power LSI circuits is increasingly becoming a severe challenge, especially for at-speed scan testing where a transition is launched at the output of a flip-flop and the corresponding circuit response is captured by a flip-flop within a functional clock cycle in order to test for delay defects. The culprit is excessively high test power compared with functional power, caused by the significant difference between test and functional data and clocking schemes. Excessive test power may cause die/package damage due to excessive heat as well as undue yield loss due to excessive power supply noise on path delay and/or clock trees, as illustrated in the following figure. As a result, it has become imperative to apply power-aware testing to low-power LSI circuits. In order words, low-power LSI circuits cannot be successfully realized without effective and efficient power-aware testing solutions. This paper will highlight three major test-power-induced problems (namely heat, false failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research topics in this field will also be discussed.
Assoc. Prof. Chaomin Luo
University of Detroit Mercy, USA
Biography: Dr. Chaomin Luo received his Ph.D. degree in Department of Electrical and Computer Engineering at the University of Waterloo, Canada in 2008, earned his M.Sc. degree in Engineering Systems and Computing at the University of Guelph, Canada, and his B.Eng. degree in Electrical Engineering from the Southeast University, Nanjing, China. He is currently an Associate Professor, in Department of Electrical and Computer Engineering, at the University of Detroit Mercy, Michigan, USA.
His research interests, of cross-disciplinary and multi-disciplinary, lie in two areas. One is in embedded systems, VLSI physical design automation, intelligence systems, VLSI CAD, optimization for VLSI design automation. The other is in robotics and automation. He was internationally recognized as a pioneer to apply Semi-definite Programming and Second Order Cone Programming into VLSI optimization design. He was awarded Faculty Research Awards in 2009, 2010, 2014 2015, and 2016 at University of Detroit Mercy, Michigan, USA.
Dr. Luo was the General Co-Chair of the 1st IEEE International Workshop on Computational Intelligence in Smart Technologies (IEEE-CIST 2015), and Journal Special Issues Chair, IEEE 2016 International Conference on Smart Technologies (IEEE-SmarTech), Cleveland, OH, USA. He was the Publicity Chair in the 2011 IEEE International Conference on Automation and Logistics. He was on the Conference Committee in the 2012 International Conference on Information and Automation and International Symposium on Biomedical Engineering and also the Publicity Chair in the 2012 IEEE International Conference on Automation and Logistics. Also, he was Chair and Vice Chair of IEEE SEM - Computational Intelligence Chapter and is currently a Chair of IEEE SEM - Computational Intelligence Chapter and Chair of Education Committee of IEEE SEM. He has delivered some presentations as a keynote speaker in some conferences, such as 2016 International Conference on Artificial Intelligence and Computer Science, etc.
Dr. Luo serves as the Editorial Board Member of International Journal of Complex Systems – Computing, Sensing and Control; Associate Editor of International journal of Robotics and Automation (IJRA); Associate Editor of International Journal of Swarm Intelligence Research (IJSIR). He has organized and chaired several special sessions on topics of Intelligent Vehicle Systems and Bio-inspired Intelligence in IEEE reputed international conferences such as IEEE-IJCNN, IEEE-SSCI, etc. He has extensively published in reputed journal and conference proceedings, such as IEEE Transactions on Neural Networks, IEEE Transactions on SMC, IEEE Transactions on Cybernetics, IEEE-ICRA, and IEEE-IROS, etc. He was the Panelist in the Department of Defense, USA, 2015-2016, 2016-2017 NDSEG Fellowship program, and National Science Foundation, USA, GRFP program, 2016-2017.